Imperas simulation technology and RISC-V reference models are now available pre-integrated into Valtrix STING to address the growing global market for RISC-V processor verification. Verification includes a design to be tested, a reference model for comparison and tests to fully exercise the design. Coverage and requirements objectives, including asynchronous events, debug modes, and the resolution analysis process are detailed in a verification plan. User controls for each test parameter allow each test condition to be matched to a particular test configuration for the device under test (DUT). Dynamic testing ensures greater reliability for targeted test suites and interactions with asynchronous events. Dynamic testing teams analyze bugs and then adapt test cases to detect other problems.
RISC-V's flexibility enables specific functionality that can be fine-tuned to key application requirements
The adoption of RISC-V for design is pushing SoC teams to adapt their verification and test plans to also cover the full range of processor DV tasks. The verification tasks for specialty processors are shifting from a few consumer IP vendors to all SoC teams. This leads efficiency goals to improve the DV analysis and resolution process to match the processor core schedule to the target SoC design.
“The flexibility of RISC-V helps us address domain-specific requirements with custom processors that go beyond the roadmap of the mainstream IP providers,” said Richard Bohn, Engineering Director at Seagate Technology, the world’s leading manufacturer of hard drives. “Designing a high-performance RISC-V processor that achieved up to 3x the performance in critical workloads was no small feat. We needed to balance the features and options with the verification implications. The combined solution of Imperas golden reference models and Valtrix STING has helped us to achieve our verification and schedule goals.”
