The new release enhances the SDAccel integrated development environment (IDE), extends OpenCL standard compliance, and features an expanded ecosystem of SDAccel development environment-certified Alliance Members providing platforms, libraries, and design services.
SDAccel Development Environment Enhancements
The SDAccel development environment 2015.1 release provides new ease-of-use enhancements to the Eclipse-based SDAccel IDE including new debug and profiling features to accelerate the development and deployment of OpenCL, C, and C++ kernels.
In addition, the release expands on SDAccel development environment Khronos standard compliance with support for a new OpenCL Installable Client Driver (ICD). With the ICD extension, multiple implementations of OpenCL can co-exist on the same system, enabling applications developers to select real-time between CPUs, GPUs and FPGAs for run time acceleration and power savings. "Bitfusion maximizes performance of existing data center applications through a combination of hardware accelerators, unique software abstractions and libraries. While we enable 'plug and play' acceleration, we also depend heavily on the underlying vendor hardware and tools to deliver high levels of performance," said Subbu Rama, CEO of Bitfusion.io, Inc.
"As users of the Xilinx Kintex® UltraScale™ FPGAs and the SDAccel development environment, we have been happy with the evolution of the environment and the great support provided by Xilinx to demonstrate OpenCL FPGA acceleration for applications in bioinformatics, scientific computing, search, computer vision, and media encoding."
Expanded Ecosystem for Platforms, Libraries, and Design Services Providers
Building on the SDAccel development environment-certified ecosystem announced in November 2014, Xilinx has welcomed new Alliance members offering development boards, market-specific libraries, and design services. New development boards include the Xilinx Kintex® UltraScale™ KCU105 Evaluation Kit, the Micron Pico Computing SB-850 board with support for Hybrid Memory Cube (HMC), the Alpha Data ADM-PCIE-KU3 board and the 4DSP CES820 commercial-off-the-shelf (COTS) compact embedded system.
New and updated Xilinx optimized libraries include OpenCV, BLAS, and machine learning deep neural network (DNN) libraries from Auviz Systems. Additionally, machine learning libraries are also available from new Alliance member, ArrayFire.
"ArrayFire is known for its 'blazing fast' software library for GPU computing. Just a few lines of code from the ArrayFire libraries replaces dozens of lines of raw code, saving valuable time and lowering development costs" said John Melonakos, CEO of ArrayFire.
"We have partnered with Xilinx to leverage our domain expertise with the SDAccel development environment to now offer a machine learning library and design services for data center FPGA-based OpenCL application acceleration." In addition to accelerating end application development of algorithms, libraries and FPGA-based kernels, Xilinx formed a global ecosystem of design services Alliance Members providing design teams around the world with the ability to leverage FPGA-based acceleration of their OpenCL, C and C++ applications. New design services members include ArrayFire, Cluster Technology Limited, Impulse Accelerated Technologies, Instigate Design, Irish Centre for High-End Computing (ICHEC), and MulticoreWare, Inc.
